A testing apparatus has conventionally been used for applying a test signal to a device under test in the case of semiconductor device testing. When the device being tested by this testing apparatus is provided with a plurality of terminals, it is sometimes necessary for the test signal to be applied to each of the plurality of terminals at a consistent timing.
FIG. 1 shows an example of the structure of the testing apparatus 10 according to the background art of the present invention. The testing apparatus 10 performs testing of the DUT (Device Under Test: device being tested) 130 by applying a test signal to each of a plurality of terminals of the DUT 130. The testing apparatus 10 is provided with a timing generator 100, a plurality of test boards 110, and a plurality of transmission channels 120. The timing generator 100 generates a timing signal indicating the timing at which the test signal is applied to the DUT 130, and feeds the timing signal to each of the plurality of test boards 110. Each of the plurality of test boards 110 is provided so as to correspond to one of the plurality of terminals of the DUT 130, and has a timing delay unit 112 for delaying the timing signal generated by the timing generator 100, and a driver 114 for applying the test signal to corresponding one of the terminals of the DUT 130 via a transmission channel 120 at the timing indicated by the timing signal thus delayed.
The plurality of drivers 114 each have varying characteristics, and since the transmission channel length is not necessarily the same in each of the plurality of transmission channels 120, there is sometimes variation in the timing at which the test signals are applied to the DUT 130 by the plurality of drivers 114. Therefore, the waveform of the test signal applied to the DUT 130 by each of the plurality of drivers 114 is observed using an oscilloscope on the point nearest to the DUT 130. The timing at which the test signal is applied to the DUT 130 by each of the plurality of drivers 114 is synchronized based on the observed waveform by calibrating the delay time caused in the timing signal by the plurality of timing delay units 112.
FIG. 2 shows the structure of a testing apparatus 20 according to the background art of the present invention. The testing apparatus 20 performs testing of the DUT by applying a test signal to each of a plurality of terminals of the DUT. The testing apparatus 20 is provided with a timing generator 200, a plurality of test boards 210, a plurality of transmission channels 215, and a calibration apparatus 220. The timing generator 200 generates a timing signal indicating the timing at which the test signal is applied to the DUT, and feeds the timing signal to each of the plurality of test boards 210. The timing generator 200 also generates a strobe signal and feeds the strobe signal to the calibration apparatus 220. Each of the plurality of test boards 210 is provided so as to correspond to one of the plurality of terminals of the DUT, and has a timing delay unit 212 for delaying the timing signal generated by the timing generator 200, and a driver 214 for applying the test signal to corresponding one of the terminals via a transmission channel 215 at the timing indicated by the timing signal thus delayed.
The calibration apparatus 220 has a comparator 222, a determination part 224, and a timing calibration part 226. The comparator 222 acquires in place of the DUT the test signal outputted by each of the plurality of drivers 214, compares the test signal thus acquired with a reference voltage VREF, and outputs the comparison result to the determination part 224. The determination part 224 detects the comparison result outputted by the comparator 222 at the timing indicated by the strobe signal generated by the timing generator 200, and determines whether the voltage of the test signal matches the reference voltage VREF at that timing. The timing calibration part 226 synchronizes the timing at which the test signal is applied to the DUT by each of the plurality of drivers 214, by calibrating the test signals applied to the DUT by each of the plurality of drivers 214 by calibrating the delay time caused in the timing signal by the plurality of timing delay units 212, based on the timing at which it is determined in the determination part 224 that the voltage of the test signal matches the reference voltage VREF.
Drawbacks are known to occur in the conventional testing apparatus for testing a DUT by applying test signals to the DUT whereby the high frequency components of the test signals are attenuated by resistance in the transmission channels and other effects, and test signals having waveforms different from desired waveforms are applied to the DUT. Techniques have been proposed for overcoming these drawbacks by using an oscilloscope to acquire waveforms of the test signals outputted by the testing apparatus and correcting the waveforms of the test signals based on the acquired waveforms (see the specification of International Patent Application Laid Open No. 03/044550, for example).